Design Center(s)

Location:Vorago, Austin TX
Line: Vorago Patented HARDSIL Technology
Flow: Q and V

Wafer Fabrication Operation(s)

Location:TSMC, Hsinchu Taiwan
Line: 8" Wafer
Flow: Fab 6 (last time buy) (0.13u CL013LP FSGe

Location:HiRel Labs, Spokane WA
Line: Wafer Lot Acceptance
Flow: V

Location:Infineon, Dallas TX
Line: Cypress
Flow: TI DMOS 5 Fab

Assembly Operation(s)

Location:Golden Altos, Fremont CA
Line: Ceramic with solder seal
Flow: Q and V

Electrical Test Operation(s)

Location:iTest, Milpitas CA
Line: Electrical Test
Flow: Q and V

Location:Eurofin EAG, Santa Clara CA
Line: Electrical Test
Flow: Q and V

Location:Golden Altos, Fremont CA
Line: Enviromental and Screening
Flow: Q and V

Location:Vorago, Austin TX
Line: QCI Coverage Tracking
Flow: Q and V